You write: "Server-based chipsets starting with the Intel Ivy Bridge (IVB) chipset provide support for pTRR. Subsequently, Haswell (HSW) and Broadwell (BSW) server chipsets from Intel also included support for the Joint Electron Design Engineering Council (JEDEC) Targeted Row Refresh (TRR) algorithm."

Can you cite a reference for that?

I think the only public source I have found on (p)TRR support in CPUs' memory controllers is this presentation:

http://infobazy.gda.pl/2014/pliki/prezentacje/d2s2e4-Kaczmarski-Optymalna.pdf
-- "Thoughts on Intel Xeon E5-2600 v2 Product Family Performance Optimisation -- component selection guidelines", August 2014, Marcin Kaczmarski.

It says: "The Pseudo Target Row Refresh (pTRR) feature introduced on Ivy Bridge processor families (2S/4S E5 v2, E7 v2) helps mitigate the DDR3 pass gate issue by automatically refreshing victim rows."

However, this is only a presentation and it's not published on an Intel site. I don't know how authoritative it is, and it doesn't provide much detail.