Love this blog format, the style of storytelling. Well done.

(Note although speaking for myself only I work in Hewlett Packard's network business, and before that in storage, and before that in servers.)

One nuance I'd encourage you to rework: the MMU itself is a very fast but very focused chunk of silicon in what now as a network person I'd call the data plane. Keeping track of free pages, making decisions on what hasn't been used recently so can be moved to disk to free up space, is done in the operating system by the memory manager, or in networking terms it is done by the control plane. This is not unlike software learning of MAC addresses.

The primary role of the MMU is multitenancy: memory owned by this process (especially the kernel) can't be read or written by any other process. A secondary role is translating the CPU's "physical address" into a particular DRAM or row of DRAMs on a particular DIMM. Different processor designs may partition these functions and use various names for parts, but I think you correctly abstracted the data plane functions as "MMU".

The primary role of the IO MMU is making memory access default-deny to I/O cards. It creates not just address mappings, but also opens up specific memory windows for a specific I/O cards to read or write.

So my nerd recommendation as a 30 years ago CPU designer is to rework slides 7-9 and 17, either separating the CPU's hardware MMU from the operating system's "memory manager" in the discussion, or inventing a generic term to include both.

@FStevenChalmers